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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
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Advance Information
8M Late Write HSTL
The MCM63L836A/918A is an 8M-bit synchronous late write fast static RAM designed to provide high performance in secondary cache and ATM switch, Telecom, and other high speed memory applications. The MCM63L918A (organized as 512K words by 18 bits) and the MCM63L836A (organized as 256K words by 36 bits) are fabricated in Motorola's high performance silicon gate copper CMOS technology. The differential clock (CK) inputs control the timing of read/write operations of the RAM. At the rising edge of CK, all addresses, write enables, and synchronous selects are registered. An internal buffer and special logic enable the memory to accept write data on the rising edge of CK, a cycle after address and control signals. Read data is available at the falling edge of CK. The RAM uses HSTL inputs and outputs. The adjustable input trip-point (Vref) and output voltage (VDDQ) gives the system designer greater flexibility in optimizing system performance. The synchronous write and byte enables allow writing to individual bytes or the entire word. The impedance of the output buffers is programmable, allowing the outputs to match the impedance of the circuit traces which reduces signal reflections. * * * * * * * * * * Byte Write Control Single 3.3 V 10% Operation HSTL -- I/O (JEDEC Standard JESD8-6 Class I Compatible) HSTL -- User Selectable Input Trip-Point HSTL -- Compatible Programmable Impedance Output Drivers Register to Latch Synchronous Operation Boundary Scan (JTAG) IEEE 1149.1 Compatible Differential Clock Inputs Optional x18 or x36 Organization MCM63L836A / 918A-3.8 = 3.8 ns MCM63L836A / 918A-4.0 = 4.0 ns MCM63L836A / 918A-4.2 = 4.2 ns MCM63L836A / 918A-4.5 = 4.5 ns MCM63L836A / 918A-5.0 = 5.0 ns * Sleep Mode Operation (ZZ Pin) * 119-Bump, 50 mil (1.27 mm) Pitch, 14 mm x 22 mm Flipped Chip Plastic Ball Grid Array (PBGA) Package
MCM63L836A MCM63L918A
FC PACKAGE PBGA CASE 999D-01
This document contains information on a new product. Specifications and information herein are subject to change without notice.
8/4/99
(c) Motorola, Inc. 1999 MOTOROLA FAST SRAM
MCM63L836A*MCM63L918A 1
FUNCTIONAL BLOCK DIAGRAM
DATA IN REGISTER DQ DATA OUT LATCH
SA
ADDRESS REGISTERS
MEMORY ARRAY
SW SBx
SW REGISTERS
CONTROL LOGIC
CK G SS REGISTERS
SS
PIN ASSIGNMENTS TOP VIEW MCM63L836A
1 A B C D E DQc F G DQc H DQc J K L DQd M VDDQ DQd N P R T NC U NC SA TDI SA TCK SA TDO NC ZZ U VDDQ TMS NC VDDQ DQd DQd NC DQd DQd SA VSS VSS VSS VDD SW SA SA VDD VSS VSS VSS VSS DQa VDDQ DQa DQa SA DQa DQa NC N P R T NC SA SA TDI NC TCK SA TDO SA ZZ VDDQ TMS NC VDDQ DQd SBd CK SBa DQa DQa M VDDQ DQb DQb NC NC NC DQb SA VSS VSS VSS VDD SW SA SA VDD VSS VSS VSS VSS NC VDDQ DQa NC SA NC DQa NC DQc VSS Vref VSS NC VDD CK VSS Vref VSS DQb DQb J K L VDDQ VDD DQd DQd VDD VDDQ DQa DQa DQc SBc NC SBb DQb DQb H DQb NC VSS Vref VSS VSS NC VDD CK CK VSS Vref VSS SBa DQa NC VDDQ VDD NC DQb DQb NC VDD VDDQ NC DQa DQa NC DQc VSS VSS SS G VSS VSS DQb DQb F G NC DQb SBb NC VSS NC DQa VDDQ DQc DQb VDDQ VDDQ NC NC DQc 2 SA NC SA DQc 3 SA SA SA VSS 4 NC NC VDD ZQ 5 SA SA SA VSS 6 SA SA SA DQb 7 VDDQ NC NC DQb A B C D E NC VDDQ DQb NC VSS VSS SS G VSS VSS NC DQa DQa VDDQ 1 VDDQ NC NC DQb 2 SA NC SA NC
MCM63L918A
3 SA SA SA VSS 4 NC NC VDD ZQ 5 SA SA SA VSS 6 SA SA SA DQa 7 VDDQ NC NC NC
MCM63L836A*MCM63L918A 2
MOTOROLA FAST SRAM
MCM63L836A PIN DESCRIPTIONS
PBGA Pin Locations 4K 4L (a) 6K, 7K, 6L, 7L, 6M, 6N, 7N, 6P, 7P (b) 6D, 7D, 6E, 7E, 6F, 6G, 7G, 6H, 7H (c) 1D, 2D, 1E, 2E, 2F, 1G, 2G, 1H, 2H (d) 1K, 2K, 1L, 2L, 2M, 1N, 2N, 1P, 2P 4F 2A, 3A, 5A, 6A, 3B, 5B, 6B, 2C, 3C, 5C, 6C, 4N, 4P, 2R, 6R, 3T, 4T, 5T 5L, 5G, 3G, 3L (a), (b), (c), (d) 4E 4M 4U 3U 5U 2U 4D 7T 4C, 2J, 4J, 6J, 4R, 3R 1A, 7A, 1F, 7F, 1J, 7J, 1M, 7M, 1U, 7U 3J, 5J 3D, 5D, 3E, 5E, 3F, 5F, 3H, 5H, 3K, 5K, 3M, 5M, 3N, 5N, 3P, 5P, 5R 4A, 1B, 2B, 4B, 7B, 1C, 7C, 4G, 4H, 1R, 7R, 1T, 2T, 6T, 6U Symbol CK CK DQx Type Input Input I/O Description Address, data in, and control input register clock. Active high. Address, data in, and control input register clock. Active low. Synchronous Data I/O.
G SA SBx
Input Input Input
Output Enable functionality not supported. Must be tied to VSS or driven to VIL max. Synchronous Address Inputs: Registered on the rising clock edge. Synchronous Byte Write Enable: Enables writes to byte x in conjunction with the SW input. Has no effect on read cycles, active low. Synchronous Chip Enable: Registered on the rising clock edge, active low. Synchronous Write: Registered on the rising clock edge, active low. Writes all enabled bytes. Test Clock (JTAG). Test Data In (JTAG). Test Data Out (JTAG). Test Mode Select (JTAG). Programmable Output Impedance: Programming pin. Enables sleep mode, active high. Core Power Supply. Output Power Supply: Provides operating power for output buffers. Input Reference: Provides reference voltage for input buffers. Ground. No Connection: There is no connection to the chip.
SS SW TCK TDI TDO TMS ZQ ZZ VDD VDDQ Vref VSS NC
Input Input Input Input Output Input Input Input Supply Supply Supply Supply --
MOTOROLA FAST SRAM
MCM63L836A*MCM63L918A 3
MCM63L918A PIN DESCRIPTIONS
PBGA Pin Locations 4K 4L (a) 6D, 7E, 6F, 7G, 6H, 7K, 6L, 6N, 7P (b) 1D, 2E, 2G, 1H, 2K, 1L, 2M, 1N, 2P 4F 2A, 3A, 5A, 6A, 3B, 5B, 6B, 2C, 3C, 5C, 6C, 4N, 4P, 2R, 6R, 2T, 3T, 5T, 6T 5L, 3G (a), (b) 4E 4M 4U 3U 5U 2U 4D 7T 4C, 2J, 4J, 6J, 4R, 3R 1A, 7A, 1F, 7F, 1J, 7J, 1M, 7M, 1U, 7U 3J, 5J 3D, 5D, 3E, 5E, 3F, 5F, 5G, 3H, 5H, 3K, 5K, 3L, 3M, 5M, 3N, 5N, 3P, 5P, 5R 4A, 1B, 2B, 4B, 7B, 1C, 7C, 2D, 7D, 1E, 6E, 2F, 1G, 4G, 6G, 2H, 4H, 7H, 1K, 6K, 2L, 7L, 6M, 2N, 7N, 1P, 6P, 1R, 7R, 1T, 4T, 6U Symbol CK CK DQx G SA SBx Type Input Input I/O Input Input Input Description Address, data in, and control input register clock. Active high. Address, data in, and control input register clock. Active low. Synchronous Data I/O. Output Enable functionality not supported. Must be tied to VSS or driven to VIL max. Synchronous Address Inputs: Registered on the rising clock edge. Synchronous Byte Write Enable: Enables writes to byte x in conjunction with the SW input. Has no effect on read cycles, active low. Synchronous Chip Enable: Registered on the rising clock edge, active low. Synchronous Write: Registered on the rising clock edge, active low. Writes all enabled bytes. Test Clock (JTAG). Test Data In (JTAG). Test Data Out (JTAG). Test Mode Select (JTAG). Programmable Output Impedance: Programming pin. Enables sleep mode, active high. Core Power Supply. Output Power Supply: Provides operating power for output buffers. Input Reference: Provides reference voltage for input buffers. Ground. No Connection: There is no connection to the chip.
SS SW TCK TDI TDO TMS ZQ ZZ VDD VDDQ Vref VSS NC
Input Input Input Input Output Input Input Input Supply Supply Supply Supply --
MCM63L836A*MCM63L918A 4
MOTOROLA FAST SRAM
ABSOLUTE MAXIMUM RATINGS (Voltages Referenced to VSS, See Note)
Rating Core Supply Voltage Output Supply Voltage Voltage On Any Pin Other Than JTAG Voltage On Any JTAG Pin Input Current (per I/O) Output Current (per I/O) Operating Temperature Temperature Under Bias Storage Temperature Symbol VDD VDDQ Vin VJTAG Iin Iout TA Tbias Tstg Value -0.5 to 3.9 -0.5 to 2.5 -0.5 to 2.5 -0.5 to 3.9 50 25 0 to 70 -10 to 85 -55 to 125 Unit V V V V mA mA C C C This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high-impedance circuit. This CMOS memory circuit has been designed to meet the dc and ac specifications shown in the tables, after thermal equilibrium has been established. This device contains circuitry that will ensure the output devices are in High-Z at power up.
NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for extended periods of time could affect device reliability.
PBGA PACKAGE THERMAL CHARACTERISTICS
Rating Junction to Ambient (Still Air) Junction to Ambient (@200 ft/min) Junction to Ambient (@200 ft/min) Junction to Board (Bottom) Junction to Case (Top) Single-Layer Board Four-Layer Board Symbol RJA RJA RJA RJB RJC Max 50 39 27 23 1 Unit C/W C/W C/W C/W C/W Notes 1, 2 1, 2 3 4 5
NOTES: 1. Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. 2. Per SEMI G38-87. 3. Measured using a four-layer test board with two internal planes. 4. Indicates the average thermal resistance between the die and the printed circuit board as measured by the ring cold plate method. 5. Indicates the average thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1).
CLOCK TRUTH TABLE
K, CLK L-H L-H L-H L-H L-H L-H L-H L-H X ZZ L L L L L L L L H SS L L L L L L L H X SW H L L L L L L X X SBa X L H H H L H X X SBb X H L H H L H X X SBc X H H L H L H X X SBd X H H H L L H X X DQ (n) Dout 0 - 35 High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z DQ (n + 1) X DIn 0 - 8 DIn 9 - 17 DIn 18 - 26 DIn 27 - 35 DIn 0 - 35 High-Z X High-Z Mode Read Cycle All Bytes Write Cycle 1st Byte Write Cycle 2nd Byte Write Cycle 3rd Byte Write Cycle 4th Byte Write Cycle All Bytes Abort Write Cycle Deselect Cycle Sleep Mode
MOTOROLA FAST SRAM
MCM63L836A*MCM63L918A 5
DC OPERATING CONDITIONS AND CHARACTERISTICS
(3.0 V VDD 3.6 V, 0C TA 70C, Unless Otherwise Noted) RECOMMENDED OPERATING CONDITIONS (See Notes 1 through 4)
Parameter Core Power Supply Voltage Output Driver Supply Voltage AC Supply Current (Device Selected, All Outputs Open, Freq = Max, VDD = Max, VDDQ = Max). Includes Supply Currents for VDD. Quiescent Active Power Supply Current (Device Selected, All Outputs Open, Freq = 0, VDD = Max, VDDQ = Max). Includes Supply Currents for VDD. Active Standby Power Supply Current (Device Deselected, Freq = Max, VDD = Max, VDDQ = Max). CMOS Standby Supply Current (Device Deselected, Freq = 0, VDD = Max, VDDQ = Max, All Inputs Static at CMOS Levels). Sleep Mode Current (ZZ = VIH, VDD = Max, VDDQ = Max) Input Reference DC Voltage Symbol VDD VDDQ IDD1 Min 3.0 1.8 -- Max -3.8 -- -- 600 Max -4.0 -- -- 580 Max -4.2 -- -- 560 Max -4.5 -- -- 540 Max -5.0 -- -- 520 Max 3.6 2.0 600 Unit V V mA 5 Notes
IDD2
--
175
175
175
175
175
175
mA
6
ISB1
--
200
195
190
185
180
200
mA
7
ISB2
--
175
175
175
175
175
175
mA
6, 7
IZZ Vref (dc)
-- 0.7
45 --
45 --
45 --
45 --
45 --
45 1.0
mA V
6, 7 8
NOTES: 1. All data sheet parameters specified to full range of VDD unless otherwise noted. All voltages are referenced to voltage applied to VSS bumps. 2. Supply voltage applied to VDD connections. 3. Supply voltage applied to VDDQ connections. 4. All power supply currents measured with outputs open or deselected. 5. All inputs are zero. 6. CMOS levels for I/Os are VIC VSS + 0.2 V or VDDQ - 0.2 V. 7. Device deselected as defined by the Clock Truth Table. 8. Although considerable latitude in the selection of the nominal dc value (i.e., rms value) of Vref is supported, the peak-to-peak ac component superimposed on Vref may not exceed 5% of the dc component of Vref.
DC INPUT CHARACTERISTICS
Parameter DC Input Logic High DC Input Logic Low Input Leakage Current Clock Input Signal Voltage Clock Input Differential Voltage (See Figure 3) Clock Input Common Mode Voltage Range (See Figure 3) Symbol VIH (dc) VIL (dc) Ilkg(I) Vin (dc) VDIF (dc) VCM (dc) Min Vref + 0.1 -0.3 -- -0.3 0.2 0.60 Max VDDQ + 0.3 Vref - 0.1 5 2.5 2.5 1.1 Unit V V A V V V 4 5 1 2, 3 Notes
NOTES: 1. Inputs may undershoot to -1.5 V (peak) for up to 35% tKHKH (e.g., 1.5 ns at a clock cycle time of 4.4 ns). See Figure 2. 2. 0 V Vin VDDQ for all pins. 3. Measured at Vref = 0.75 V. 4. Minimum instantaneous differential input voltage required for differential input clock operation. 5. Maximum rejectable common mode input voltage variation.
MCM63L836A*MCM63L918A 6
MOTOROLA FAST SRAM
DC OUTPUT BUFFER CHARACTERISTICS -- PROGRAMMABLE IMPEDANCE PUSH-PULL OUTPUT BUFFER MODE
(3.0 V VDD 3.6 V, 0C TA 70C, ZQ = IZQ (out) (RQ)) (See Notes 1 and 2) Parameter Output Logic Low Output Logic High Light Load Output Logic Low Light Load Output Logic High Programmable Impedance Symbol IOL IOH VOL VOH ZQ Min (VDDQ/2) / [(RQ/5) + 10%] (VDDQ/2) / [(RQ/5) + 10%] VSS VDDQ - 0.4 [(RQ/5) - 10%] Max (VDDQ/2) / [(RQ/5) - 10%] (VDDQ/2) / [(RQ/5) - 10%] 0.4 VDDQ [(RQ/5) + 10%] Unit A A V V Notes 3 4 5 6 7
NOTES: 1. The impedance controlled mode is expected to be used in point-to-point applications, driving high-impedance inputs. 2. The ZQ pin is connected through RQ to VSS for the controlled impedance mode. 3. VOL = VDDQ/2. 4. VOH = VDDQ/2. 5. IOL 100 A. 6. | IOH | 100 A. 7. 175 RQ 375.
DC OUTPUT BUFFER CHARACTERISTICS -- MINIMUM IMPEDANCE PUSH-PULL OUTPUT BUFFER MODE
(3.0 V VDD 3.6 V, 0C TA 70C) (See Notes 1 and 2) Parameter Output Logic Low Output Logic High Light Load Output Logic Low Symbol VOL2 VOH2 VOL3 Min VSS VDDQ - 0.4 VSS Max 0.4 VDDQ 0.2 Unit V V V Notes 3 4 5
Light Load Output Logic High VOH3 VDDQ - 0.2 VDDQ V 6 NOTES: 1. The push-pull output mode is expected to be used in bussed applications and may be series or parallel terminated. Conforms to the JEDEC Standard JESD8-6 Class I. 2. The ZQ pin is connected to a 100 resistor to VSS to enable the minimum impedance mode. 3. IOL 8 mA. 4. | IOH | 8 mA. 5. IOL 100 A. 6. | IOH | 100 A.
CAPACITANCE (f = 1.0 MHz, dV = 30 mV, 3.0 V VDD 3.6 V, 0C TA 70C, Periodically Sampled Rather Than 100% Tested)
Characteristic Input Capacitance Input/Output Capacitance CK, CK Capacitance Symbol Cin CI/O CCK Typ 3.2 3.8 3.7 Max 5 6 5 Unit pF pF pF
MOTOROLA FAST SRAM
MCM63L836A*MCM63L918A 7
AC OPERATING CONDITIONS AND CHARACTERISTICS
(0C TA 70C, Unless Otherwise Noted)
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.25 to 1.25 V Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . 1 V/ns (20% to 80%) Input Timing Measurement Reference Level . . . . . . . . . . . . . . 0.75 V Output Timing Reference Level . . . . . . . . . . . . . . . . . . . . . . . . . 0.75 V Clock Input Timing Reference Level . . . . . . Differential Cross-Point ZQ for 50 Impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 RJA Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27C/W
READ/WRITE CYCLE TIMING
63L836A-3.8 63L918A-3.8 Parameter P Cycle Time Clock High Pulse Width Clock Low Pulse Width Clock High to Output Valid Clock Low to Output Valid Clock Low to Output Hold Clock Low to Output Low-Z Clock High to Output High-Z ZZ High to Sleep Mode ZZ Low to Recovery Setup Times: Address Data In Chip Select Write Enable Address Data In Chip Select Write Enable Symbol S bl tKHKH tKHKL tKLKH tKHQV tKLQV tKLQX tKLQX1 tKHQZ tZZE tZZR tAVKH tDVKH tSVKH tWVKH tKHAX tKHDX tKHSX tKHWX Min 3.8 1.5 1.5 -- -- 0.7 0.7 0.7 3.0 -- 0.4 Max -- -- -- 3.8 1.7 -- -- 1.7 -- 10.0 -- 63L836A-4.0 63L918A-4.0 Min 4.0 1.6 1.6 -- -- 0.7 0.7 0.7 3.0 -- 0.4 Max -- -- -- 4.0 1.8 -- -- 1.8 -- 10.0 -- 63L836A-4.2 63L918A-4.2 Min 4.2 1.6 1.6 -- -- 0.7 0.7 0.7 3.0 -- 0.4 Max -- -- -- 4.2 1.9 -- -- 1.9 -- 10.0 -- 63L836A-4.5 63L918A-4.5 Min 4.5 1.6 1.6 -- -- 0.7 0.7 0.7 3.0 -- 0.4 Max -- -- -- 4.5 2.0 -- -- 2.0 -- 10.0 -- 63L836A-5.0 63L918A-5.0 Min 5.0 2.0 2.0 -- -- 0.7 0.7 0.7 3.0 -- 0.4 Max -- -- -- 5.0 2.2 -- -- 2.2 -- 10.0 -- Unit Ui ns ns ns ns ns ns ns ns ns ns ns 1 1, 2 1, 2 Notes N
Hold Times:
0.8
--
0.8
--
0.8
--
0.8
--
0.8
--
ns
NOTES: 1. This parameter is sampled and not 100% tested. 2. Measured at 200 mV from steady state.
TIMING LIMITS
0.75 V Vref DEVICE UNDER TEST ZQ 50 250 VDDQ/2 50 The table of timing values shows either a minimum or a maximum limit for each parameter. Input requirements are specified from the external system point of view. Thus, address setup time is shown as a minimum since the system must supply at least that much time. On the other hand, responses from the memory are specified from the device point of view. Thus, the access time is shown as a maximum since the device never provides data later than that time.
Figure 1. AC Test Load
MCM63L836A*MCM63L918A 8
MOTOROLA FAST SRAM
AC INPUT CHARACTERISTICS
Parameter AC Input Logic High (See Figure 4) AC Input Logic Low (See Figures 2 and 4) Input Reference Peak-to-Peak AC Voltage Clock Input Differential Voltage Symbol VIH (ac) VIL (ac) Vref (ac) Vdif (ac) Min Vref + 200 mV -- -- 400 mV Max -- Vref - 200 mV 5% Vref (dc) VDDQ + 600 mV Notes 1 2 3 4
NOTES: 1. Inputs may overshoot to VDD + 1 V for 30% tKHKH or 1.5 ns, whichever is smaller, and VDD + 1.5 V peak overshoot. 2. Inputs may undershoot to VSS - 1 V for 30% tKHKH or 1.5 ns, whichever is smaller and VSS - 1.5 V peak undershoot. 3. Although considerable latitude in the selection of the nominal dc value (i.e., rms value) of Vref is supported, the peak-to-peak ac component superimposed on Vref may not exceed 5% of the dc component of Vref. 4. Minimum instantaneous differential input voltage required for differential input clock operation. VOH
VSS 50% 100% 20% tKHKH
Figure 2. Undershoot Voltage
VDDQ VTR CROSSING POINT VDIF VCP VSS * VCM, the Common Mode Input Voltage, equals VTR - [(VTR - VCP)/2]. VCM*
Figure 3. Differential Inputs/Common Mode Input Voltage
VIH(ac) Vref
VIL(ac)
Figure 4. AC Input Conditions
MOTOROLA FAST SRAM
MCM63L836A*MCM63L918A 9
REGISTER LATCH READ-WRITE-READ CYCLES
t KHKH CK t AVKH t KHAX SA A0 A1 A2 t SVKH SS t WVKH t KHWX SW A3 t KHSX t KLKH A4 t KHKL
SBx
G t KHQV t KLQV t KLQX1 DQ Q0 READ Q1 READ D2 WRITE t KHQZ t KLQX t DVKH t KHDX Q3 READ DESELECT (HIGH-Z) t KHQZ t KLQX1 Q4 READ
MCM63L836A*MCM63L918A 10
MOTOROLA FAST SRAM
EEEEEEEEEEEE EEEEEEEEEEEE EEEEEEEEEEEE EEEEEEEEEEEE EEEEEEEEEEEE EEEEEEEEEEEE EEEEEEEEEEEE
tZZE
EEEEEEEEEEEEEEEEEEE EEEEEEEEEEEEEEEEEEE EEEEEEEEEEEEEEEEEEE EEEEEEEEEEEEEEEEEEE EEEEEEEEEEEEEEEEEEE EEEEEEEEEEEEEEEEEEE EEEEEEEEEEEEEEEEEEE EEEEEEEEEEEEEEEEEEE EEEEEEEEEEEEEEEEEEE EEEEEEEEEEEEEEEEEEE EEEEEEEEEEEEEEEEEEE
I ZZ tZZR
MOTOROLA FAST SRAM
SW DQ CK ZZ G ADDR NORMAL OPERATION NO NEW READS OR WRITES ALLOWED
MCM63L836A*MCM63L918A 11
IDD IN SLEEP MODE NORMAL OPERATION
SLEEP MODE TIMING
NO READS OR WRITES ALLOWED
FUNCTIONAL OPERATION
READ AND WRITE OPERATIONS All control signals are registered on the rising edge of the CK clock. These signals must meet the setup and hold times shown in the AC Characteristics table. On the falling edge of the current cycle, the output latch becomes transparent and data is available. The output data is latched on the rising edge of the next clock. The output data is available at the output at tKLQV or tKHQV, whichever is later. tKHQV is the internal latency of the device. During this same cycle, a new read address can be applied to the address pins. A write cycle can occur on the next cycle as long as tKHQZ and tDVKH are met. Read cycles may follow write cycles immediately. SS and SW control output drive. Chip deselect via a high on SS at the rising edge of the CK clock has its effect on the output drivers immediately. SW low deselects the output drivers immediately (on the same cycle). Output selecting via a low on SS and high on SW at a rising CK clock has its effect on the output drivers at tKLQX. Output data will be valid at tKHQV or tKLQV, which is even later. Outputs will begin driving at tKLQX1. Outputs will hold previous data until tKLQX or tKHQZ in the case of a write following a read. WRITE AND BYTE WRITE FUNCTIONS Note that in the following discussion the term "byte" refers to nine bits of the RAM I/O bus. In all cases, the timing parameters described for synchronous write input (SW) apply to each of the byte write enable inputs (SBa, SBb, etc.). Byte write enable inputs have no effect on read cycles. This allows the system designer not interested in performing byte writes to connect the byte enable inputs to active low (VSS). Reads of all bytes proceed normally and write cycles, activated via a low on SW and the rising edge of CK, write the entire RAM I/O width. This way the designer is spared having to drive multiple write input buffer loads. Byte writes are performed using the byte write enable inputs in conjunction with the synchronous write input (SW). It is important to note that writing any one byte will inhibit a read of all bytes at the current address. The RAM can not
simultaneously read one byte and write another at the same address. A write cycle initiated with none of the byte write enable inputs active, is neither a read or a write. No write will occur, but the outputs will be deselected as in a normal write cycle. LATE WRITE The write address is sampled on the first rising edge of clock, and write data is sampled on the following rising edge. The late write feature is implemented with single stage write buffering. Write buffering is transparent to the user. A comparator monitors the address bus and, when necessary, routes buffer contents to the outputs to ensure coherent operation. This occurs in all cases, whether there is a byte write or a full word is written. PROGRAMMABLE IMPEDANCE OPERATION The designer can program the RAMs output buffer impedance by terminating the ZQ pin to VSS through a precision resistor (RQ). The value of RQ is five times the output impedance desired. For example, 250 resistor will give an output impedance of 50 . Impedance updates occur during write and deselect cycles. The actual change in the impedance occurs in small increments and is binary. The binary impedance has 256 values and therefore, there are no significant disturbances that occur on the output because of this smooth update method. At power up, the output impedance will take up to 65,000 cycles for the impedance to be completely updated. At recovery from sleep mode, the previously programmed value will be recovered. POWER UP AND INITIALIZATION The following supply voltage application sequence is recommended: VSS, VDD, then VDDQ. Please note, per the Absolute Maximum Ratings table, VDDQ is not to exceed VDDQ + 0.5 V or 2.5 V max, whatever the instantaneous value of VDD . Once supplies have reached specification levels, a minimum dwell of 1.0 ms with CK clock inputs cycling is required before beginning normal operations. At power up the output impedance will be set at approximately 50 as stated above.
MCM63L836A*MCM63L918A 12
MOTOROLA FAST SRAM
SLEEP MODE This device is equipped with an optional sleep or low power mode. The sleep mode pin is asynchronous and active high. During normal operation, the ZZ pin is pulled low. When ZZ is pulled high, the chip will enter sleep mode where the device will meet the lowest possible power conditions. The Sleep Mode Timing diagram shows the following modes of operation: Normal Operation, No Read/Write Allowed, and Sleep Mode. Normal Operation All inputs must meet setup and hold times prior to sleep and tZZR nanoseconds after recovering from sleep. Clock (CK) must also meet cycle high and low times during these periods. Two cycles prior to sleep, initiation of either a read or write operation is not allowed.
No Read/Write Allowed During the period of time just prior to sleep and during recovery from sleep, the assertion of any write or read signal is not allowed. If a write or read operation occurs during these periods, the memory array may be corrupted. Validity of data out from the RAM can not be guaranteed immediately after ZZ is asserted (prior to being in sleep). During sleep mode recovery, the output impedance must be given additional time above and beyond tZZR in order to match desired impedance (see explanation in Output Impedance Circuitry paragraph). Sleep Mode The RAM automatically deselects itself. The RAM disconnects its internal clock buffer. The external clock may continue to run without impacting the RAMs sleep current (IZZ). All outputs will remain in a High-Z state while in sleep mode. All inputs are allowed to toggle. The RAM will not be selected, and perform any reads or writes.
SERIAL BOUNDARY SCAN TEST ACCESS PORT OPERATION
OVERVIEW The serial boundary scan test access port (TAP) on this RAM is designed to operate in a manner consistent with IEEE Standard 1149.1-1990 (commonly referred to as JTAG), but does not implement all of the functions required for IEEE 1149.1 compliance. Certain functions have been modified or eliminated because their implementation places extra delays in the RAMs critical speed path. Nevertheless, the RAM supports the standard TAP controller architecture. The TAP controller is the state machine that controls the TAP operation and can be expected to function in a manner that does not conflict with the operation of devices with IEEE 1149.1 compliant TAPs. The TAP operates using conventional JEDEC Standard 8-1B low voltage (3.3 V) TTL/CMOS logic level signaling. DISABLING THE TEST ACCESS PORT It is possible to use this device without utilizing the TAP. To disable the TAP controller without interfering with normal operation of the device, TCK must be tied to VSS to preclude mid-level inputs. TDI and TMS are designed so an undriven input will produce a response identical to the application of a logic 1, and may be left unconnected. But they may also be tied to VDD through a 1 k resistor. TDO should be left unconnected.
TAP DC OPERATING CHARACTERISTICS
(3.0 V VDD 3.6 V, 0C TA 70C, Unless Otherwise Noted)
Parameter Logic Input Logic High Logic Input Logic Low Logic Input Leakage Current CMOS Output Logic Low CMOS Output Logic High TTL Output Logic Low TTL Output Logic High NOTES: 1. 0 V Vin VDD for all logic input pins. 2. IOL1 100 A @ VOL = 0.2 V. Sampled, not 100% tested. 3. |IOH1| 100 A @ VDDQ - 0.2 V. Sampled, not 100% tested. 4. IOL2 8 mA @ VOL = 0.4 V. 5. |IOH2| 8 mA @ VOH = 2.4 V. Symbol VIH1 VIL1 Ilkg VOL1 VOH1 VOL2 VOH2 Min 1.2 -0.3 -- -- VDD - 0.2 -- 2.4 Max VDD + 0.3 0.4 5 0.2 -- 0.4 -- Unit V V A V V V V 1 2 3 4 5 Notes
MOTOROLA FAST SRAM
MCM63L836A*MCM63L918A 13
TAP AC OPERATING CONDITIONS AND CHARACTERISTICS
(0C TA 70C, Unless Otherwise Noted)
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0 V Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . 1 V/ns (20% to 80%) Input Timing Measurement Reference Level . . . . . . . . . . . . . . . 1.5 V Output Timing Reference Level . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 V Output Test Load . . . . . 50 Parallel Terminated T-Line with 20 pF Receiver Input Capacitance Test Load Termination Supply Voltage (VT) . . . . . . . . . . . . . . . 1.5 V
TAP CONTROLLER TIMING
Parameter Cycle Time Clock High Time Clock Low Time TMS Setup TMS Hold TDI Valid to TCK High TCK High to TDI Don't Care Capture Setup Capture Hold TCK Low to TDO Unknown TCK Low to TDO Valid Symbol tTHTH tTHTL tTLTH tMVTH tTHMX tDVTH tTHDX tCS tCH tTLQX tTLOV Min 100 40 40 10 10 10 10 10 10 0 -- Max -- -- -- -- -- -- -- -- -- -- 20 Unit ns ns ns ns ns ns ns ns ns ns ns 1 1 Notes
NOTE: 1. tCS + tCH defines the minimum pause in RAM I/O pad transitions to ensure accurate pad data capture.
AC TEST LOAD
1.5 V 50 50
DEVICE UNDER TEST
TAP CONTROLLER TIMING DIAGRAM
tTHTH tTLTH TEST CLOCK (TCK) tTHTL tMVTH TEST MODE SELECT (TMS) tTHDX tDVTH TEST DATA IN (TDI) tTLQV tTLQX TEST DATA OUT (TDO) tTHMX
MCM63L836A*MCM63L918A 14
MOTOROLA FAST SRAM
TEST ACCESS PORT PINS
TCK -- TEST CLOCK (INPUT) Clocks all TAP events. All inputs are captured on the rising edge of TCK and all outputs propagate from the falling edge of TCK. TMS -- TEST MODE SELECT (INPUT) The TMS input is sampled on the rising edge of TCK. This is the command input for the TAP controller state machine. An undriven TMS input will produce the same result as a logic 1 input level. TDI -- TEST DATA IN (INPUT) The TDI input is sampled on the rising edge of TCK. This is the input side of the serial registers placed between TDI and TDO. The register placed between TDI and TDO is determined by the state of the TAP controller state machine and the instruction that is currently loaded in the TAP instruction register (see Figure 6). An undriven TDI pin will produce the same result as a logic 1 input level. TDO -- TEST DATA OUT (OUTPUT) Output that is active depending on the state of the TAP state machine (see Figure 6). Output changes in response to the falling edge of TCK. This is the output side of the serial registers placed between TDI and TDO. TRST -- TAP RESET This device does not have a TRST pin. TRST is optional in IEEE 1149.1. The test-logic reset state is entered while TMS is held high for five rising edges of TCK. Power-on reset circuitry is included internally. This type of reset does not affect the operation of the system logic. The reset affects test logic only.
passed through the RAMs TAP to another device in the scan chain with as little delay as possible. BOUNDARY SCAN REGISTER The boundary scan register is identical in length to the number of active input and I/O connections on the RAM (not counting the TAP pins). This also includes a number of place holder locations (always set to a logic 1) reserved for density upgrade address pins. There are a total of 70 bits in the case of the x36 device and 51 bits in the case of the x18 device. The boundary scan register, under the control of the TAP controller, is loaded with the contents of the RAM I/O ring when the controller is in capture-DR state and then is placed between the TDI and TDO pins when the controller is moved to shift-DR state. Several TAP instructions can be used to activate the boundary scan register. The Bump/Bit Scan Order tables describe which device bump connects to each boundary scan register location. The first column defines the bit's position in the boundary scan register. The shift register bit nearest TDO (i.e., first to be shifted out) is defined as bit 1. The second column is the name of the input or I/O at the bump and the third column is the bump number. IDENTIFICATION (ID) REGISTER The ID register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in capture-DR state with the IDCODE command loaded in the instruction register. The code is loaded from a 32-bit on-chip ROM. It describes various attributes of the RAM as indicated below. The register is then placed between the TDI and TDO pins when the controller is moved into shift-DR state. Bit 0 in the register is the LSB and the first to reach TDO when shifting begins. ID Register Presence Indicator
Bit No. Value 0 1
TEST ACCESS PORT REGISTERS
OVERVIEW The various TAP registers are selected (one at a time) via the sequences of 1s and 0s input to the TMS pin as the TCK is strobed. Each of the TAP registers are serial shift registers that capture serial input data on the rising edge of TCK and push serial data out on the subsequent falling edge of TCK. When a register is selected, it is "placed" between the TDI and TDO pins. INSTRUCTION REGISTER The instruction register holds the instructions that are executed by the TAP controller when it is moved into the run test/idle or the various data register states. The instructions are 3 bits long. The register can be loaded when it is placed between the TDI and TDO pins. The instruction register is automatically preloaded with the IDCODE instruction at power up or whenever the controller is placed in test-logic- reset state. BYPASS REGISTER The bypass register is a single bit register that can be placed between TDI and TDO. It allows serial test data to be
Motorola JEDEC ID Code (Compressed Format, per IEEE Standard 1149.1-1990)
Bit No. Value 11 0 10 0 9 0 8 0 7 0 6 0 5 0 4 1 3 1 2 1 1 0
Reserved For Future Use
Bit No. Value 17 x 16 x 15 x 14 x 13 x 12 x
Device Width
Configuration 256K x 36 512K x 18 Bit No. Value Value 22 0 0 21 0 0 20 1 0 19 0 1 18 0 1
Device Depth
Configuration 256K x 36 512K x 18 Bit No. Value Value 27 0 0 26 0 0 25 1 1 24 1 1 23 0 1
Revision Number
Bit No. Value 31 x 30 x 29 x 28 x
Figure 5. ID Register Bit Meanings
MOTOROLA FAST SRAM
MCM63L836A*MCM63L918A 15
MCM63L836A Bump/Bit Scan Order
Bit No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 Signal Name M2 SA SA SA SA ZZ DQa DQa DQa DQa DQa DQa DQa DQa DQa SBa CK CK G SBb DQb DQb DQb DQb DQb DQb DQb DQb DQb SA SA SA SA SA SA Bump ID 5R 4P 4T 6R 5T 7T 6P 7P 6N 7N 6M 6L 7L 6K 7K 5L 4L 4K 4F 5G 7H 6H 7G 6G 6F 7E 6E 7D 6D 6A 6C 5C 5A 6B 5B Bit No. 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 Signal Name SA NC SA SA SA SA DQc DQc DQc DQc DQc DQc DQc DQc DQc SBc ZQ SS NC NC SW SBd DQd DQd DQd DQd DQd DQd DQd DQd DQd SA SA SA M1 Bump ID 3B 2B 3A 3C 2C 2A 2D 1D 2E 1E 2F 2G 1G 2H 1H 3G 4D 4E 4G 4H 4M 3L 1K 2K 1L 2L 2M 1N 2N 1P 2P 3T 2R 4N 3R
MCM63L918A Bump/Bit Scan Order
Bit No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 Signal Name M2 SA SA SA SA ZZ DQa DQa DQa DQa SBa CK CK G DQa DQa DQa DQa DQa SA SA SA SA SA SA SA NC SA SA SA SA DQb DQb DQb DQb Bump ID 5R 6T 4P 6R 5T 7T 7P 6N 6L 7K 5L 4L 4K 4F 6H 7G 6F 7E 6D 6A 6C 5C 5A 6B 5B 3B 2B 3A 3C 2C 2A 1D 2E 2G 1H Bit No. 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 Signal Name SBb ZQ SS NC NC SW DQb DQb DQb DQb DQb SA SA SA SA M1 Bump ID 3G 4D 4E 4G 4H 4M 2K 1L 2M 1N 2P 3T 2R 4N 2T 3R
NOTES: 1. The NC pads listed in this table are indeed no connects, but are represented in the boundary scan register by a "place holder" bit that is forced to logic 1. These pads are reserved for use as address inputs on higher density RAMs that follow this pad out and scan order standard. 2. In scan mode, differential inputs CK and CK are referenced to each other and must be at opposite logic levels for reliable operation. 3. ZQ, M1, and M2 are not ordinary inputs and may not respond to standard I/O logic levels. ZQ, M1, and M2 must be driven to within 100 mV of a VDD or VSS supply rail to ensure consistent results. 4. ZZ must remain at VIL during boundary scan to ensure consistent results.
MCM63L836A*MCM63L918A 16
MOTOROLA FAST SRAM
TAP CONTROLLER INSTRUCTION SET
OVERVIEW There are two classes of instructions defined in IEEE Standard 1149.1-1990, the standard (public) instructions and device specific (private) instructions. Some public instructions are mandatory for IEEE 1149.1 compliance. Optional public instructions must be implemented in prescribed ways. Although the TAP controller in this device follows the IEEE 1149.1 conventions, it is not IEEE 1149.1 compliant because some of the mandatory instructions are not fully implemented. The TAP on this device may be used to monitor all input and I/O pads, but can not be used to load address, data, or control signals into the RAM or to preload the I/O buffers. In other words, the device will not perform IEEE 1149.1 EXTEST, INTEST, or the preload portion of the SAMPLE/PRELOAD command. When the TAP controller is placed in capture-IR state, the two least significant bits of the instruction register are loaded with 01. When the controller is moved to the shift-IR state, the instruction register is placed between TDI and TDO. In this state, the desired instruction is serially loaded through the TDI input (while the previous contents are shifted out at TDO). For all instructions, the TAP executes newly loaded instructions only when the controller is moved to update-IR state. The TAP instruction sets for this device are listed in the following tables.
expected. RAM input signals must be stabilized for long enough to meet the TAPs input data capture setup plus hold time (tCS plus tCH). The RAMs clock inputs need not be paused for any other TAP operation except capturing the I/O ring contents into the boundary scan register. Moving the controller to shift-DR state then places the boundary scan register between the TDI and TDO pins. Because the PRELOAD portion of the command is not implemented in this device, moving the controller to the update-DR state with the SAMPLE/PRELOAD instruction loaded in the instruction register has the same effect as the pause-DR command. This functionality is not IEEE 1149.1 compliant. EXTEST EXTEST is an IEEE 1149.1 mandatory public instruction. It is to be executed whenever the instruction register, whatever length it may be in the device, is loaded with all logic 0s. EXTEST is not implemented in this device. Therefore, this device is not IEEE 1149.1 compliant. Nevertheless, this RAM TAP does respond to an all 0s instruction, as follows. With the EXTEST (000) instruction loaded in the instruction register, the RAM responds just as it does in response to the SAMPLE/PRELOAD instruction described above, except the DQ pins are forced to High-Z any time the instruction is loaded. IDCODE
STANDARD (PUBLIC) INSTRUCTIONS
BYPASS The BYPASS instruction is loaded in the instruction register when the bypass register is placed between TDI and TDO. This occurs when the TAP controller is moved to the shift-DR state. This allows the board level scan path to be shortened to facilitate testing of other devices in the scan path. SAMPLE/PRELOAD SAMPLE/PRELOAD is an IEEE 1149.1 mandatory public instruction. When the SAMPLE/PRELOAD instruction is loaded in the instruction register, moving the TAP controller into the capture-DR state loads the data in the RAMs input and I/O buffers into the boundary scan register. Because the RAM clock(s) are independent from the TAP clock (TCK), it is possible for the TAP to attempt to capture the I/O ring contents while the input buffers are in transition (i.e., in a metastable state). Although allowing the TAP to sample metastable inputs will not harm the device, repeatable results can not be
The IDCODE instruction causes the ID ROM to be loaded into the ID register when the controller is in capture-DR mode and places the ID register between the TDI and TDO pins in shift-DR mode. The IDCODE instruction is the default instruction loaded in at power up and any time the controller is placed in the test-logic-reset state.
DEVICE SPECIFIC (PUBLIC) INSTRUCTION
SAMPLE-Z If the SAMPLE-Z instruction is loaded in the instruction register, all DQ pins are forced to an inactive drive state (High-Z) and the boundary scan register is connected between TDI and TDO when the TAP controller is moved to the shift-DR state.
DEVICE SPECIFIC (PRIVATE) INSTRUCTION
NO OP Do not use these instructions; they are reserved for future use.
MOTOROLA FAST SRAM
MCM63L836A*MCM63L918A 17
STANDARD (PUBLIC) INSTRUCTION CODES
Instruction EXTEST IDCODE SAMPLE/PRELOAD Code* 000 001** 100 Description Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Forces all DQ pins to High-Z state. NOT IEEE 1149.1 COMPLIANT. Preloads ID register and places it between TDI and TDO. Does not affect RAM operation. Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Does not affect RAM operation. Does not implement IEEE 1149.1 PRELOAD function. NOT IEEE 1149.1 COMPLIANT. Places bypass register between TDI and TDO. Does not affect RAM operation. Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Forces all DQ pins to High-Z state.
BYPASS SAMPLE-Z
111 010
* Instruction codes expressed in binary; MSB on left, LSB on right. ** Default instruction automatically loaded at power up and in test-logic-reset state.
STANDARD (PRIVATE) INSTRUCTION CODES
Instruction NO OP NO OP NO OP Code* 011 101 110 Description Do not use these instructions; they are reserved for future use. Do not use these instructions; they are reserved for future use. Do not use these instructions; they are reserved for future use.
* Instruction codes expressed in binary, MSB on left, LSB on right.
1
TEST-LOGIC RESET 0 RUN-TEST/ IDLE 1 SELECT DR-SCAN 0 1 CAPTURE-DR 0 SHIFT-IR 1 1 EXIT1-DR 0 PAUSE-DR 1 0 EXIT2-DR 1 UPDATE-DR 1 0 1 0 0 EXIT1-IR 0 PAUSE-IR 1 EXIT2-IR 1 UPDATE-IR 0 0 0 1 1 SELECT IR-SCAN 0 CAPTURE-IR 0 SHIFT-IR 1 1 0 1
0
NOTE: The value adjacent to each state transition represents the signal present at TMS at the rising edge of TCK.
Figure 6. TAP Controller State Diagram
MCM63L836A*MCM63L918A 18
MOTOROLA FAST SRAM
ORDERING INFORMATION
(Order by Full Part Number) MCM
Motorola Memory Prefix Part Number
63L836A 63L918A XX
X
X
R = Tape and Reel, Blank = Tray Speed (3.8 = 3.8 ns, 4.0 = 4.0 ns, 4.2 = 4.2 ns, 4.5 = 4.5 ns, 5.0 = 5.0 ns) Package (FC = Flipped Chip PBGA)
Full Part Numbers -- MCM63L836AFC3.8 MCM63L836AFC4.0 MCM63L836AFC4.2 MCM63L836AFC4.5 MCM63L836AFC5.0
MCM63L918AFC3.8 MCM63L918AFC4.0 MCM63L918AFC4.2 MCM63L918AFC4.5 MCM63L918AFC5.0
MCM63L836AFC3.8R MCM63L836AFC4.0R MCM63L836AFC4.2R MCM63L836AFC4.5R MCM63L836AFC5.0R
MCM63L918AFC3.8R MCM63L918AFC4.0R MCM63L918AFC4.2R MCM63L918AFC4.5R MCM63L918AFC5.0R
PACKAGE DIMENSIONS
FC PACKAGE 7 X 17 BUMP PBGA CASE 999D-01
4X
0.2 B 0.2 A 0.25 A
NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M,1992. 2. ALL DIMENSIONS IN MILLIMETERS. 3. DIMENSION b IS THE MAXIMUM SOLDER BALL DIAMETER MEASURED PARALLEL TO DATUM PLANE A. 4. DATUM A, THE SEATING PLANE, IS DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS. 5. AN AI INDEX MARK WILL BE LOCATED IN THIS AREA. 6. D2 AND E2 DEFINE THE AREA OCCUPIED BY THE DIE. D3 AND E3 ARE THE MINIMUM CLEARANCE FROM THE PACKAGE EDGE TO THE CHIP CAPACITORS. 7. CAPACITORS MAY NOT BE PRESENT ON ALL DEVICES. 8. CAUTION MUST BE TAKEN NOT TO SHORT EXPOSED METAL CAPACITOR PADS ON PACKAGE TOP. DIM A A1 A2 A3 A4 D D1 D2 D3 E E1 E2 E3 b e MILLIMETERS MIN MAX --- 2.77 0.50 0.70 1.75 2.07 0.80 0.92 0.92 1.15 22.00 BSC 20.32 BSC 12.10 12.40 1.10 14.00 BSC 7.62 BSC 7.26 7.46 1.10 0.60 0.90 1.27 BSC
C
PIN A1 INDEX
E E3
5 D3
SEATING PLANE
D2
D
0.35 A
E2 TOP VIEW E1
6X
e
U T R P N M L K J H G F E D C B A 1 2 3 45 6 7
16X
e A3 A2
A4
D1
A1 A SIDE VIEW
119X
b3 0.3 0.15
M M
BOTTOM VIEW
ABC A
MOTOROLA FAST SRAM
MCM63L836A*MCM63L918A 19
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MCM63L836A*MCM63L918A 20
MOTOROLAMCM63L836A/D FAST SRAM

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